1. Field of the Invention
The present invention relates to a Viterbi decoder for decoding a desired tree code according to a Viterbi algorithm and to a transmitting equipment for coding desired transmission information and then transmitting it to a receiving equipment that incorporates such a Viterbi decoder.
2. Description of the Related Art
Tree codes such as a convolutional code are codes with which the coding gain is kept high in a stable manner without the rate being set high by virtue of the application of a soft decision system according to a Viterbi algorithm to a receiving end even in radio transmission systems in which a high transmission rate and high transmission quality are required in spite of limitations on widening of the transmission bandwidth.
Therefore, in mobile communication systems and satellite communication systems to which such a convolutional code is used, Viterbi decoders are incorporated in many cases in terminals and other equipment that are not only required to be of a low price and a small size but also severely required to be of low power consumption.
FIG. 8 shows the configuration of an exemplary receiving part that incorporates a Viterbi decoder.
As shown in FIG. 8, a baseband signal indicating demodulated transmission information is input to a first input of a de-interleaving part 111. A clock signal (hereinafter referred to as xe2x80x9cwrite clock signalxe2x80x9d) that is synchronized with the baseband signal and a clock signal (hereinafter referred to as xe2x80x9cread clock signalxe2x80x9d) that is locally generated in a non-illustrated receiving part are supplied to second and third inputs of the de-interleaving part 111, respectively. The output of the de-interleaving part 111 is connected to the input of a branch metric obtaining part 112. The four outputs of the branch metric obtaining part 112 are connected to the corresponding inputs of an ACS-operation part 113. The first to fourth outputs of the ACS-operation part 113 are connected to a writing -port of a path memory 114. Corresponding input/outputs of a maximum likelihood decision part 115 are connected to reading ports of the path memory 114. Transmission information as a maximum likelihood decision result is obtained at the output of the maximum likelihood decision part 115.
The de-interleaving part 111 is composed of a dual port RAM 116 whose writing input is given a baseband signal (mentioned above) and whose reading output is directly connected to the input of the branch metric obtaining part 112, a counter 117W whose counting output is connected to the write address input of the dual port RAM 116 and whose counting input is given a write clock signal, and a counter 17R whose counting output is connected to the read address input of the dual port RAM 116 and whose counting input is given a read clock signal.
The branch metric obtaining part 112 is composed of branch metric computing units (BMCU) 12000, 12001, 12010, and 12011 whose inputs are connected parallel to the outputs of the de-interleaving part 111 (dual port RAM 116).
The ACS-operation part 113 is composed of adders (123001, 123012), (123011, 123012), (123101, 123102), and (123111, 123112) that are disposed at the first stage and one inputs of which are connected to the outputs of the respective branch metric computing units 12000, 12001, 12010, and 12011; a comparator (CMP) 1241 whose first and second inputs are connected to the outputs of the respective adders 123001 and 123112; a comparator (CMP) 1242 whose first and second inputs are connected to the outputs of the respective adders 123111 and 123002; a comparator (CMP) 1243 whose first and second inputs are connected to the outputs of the respective adders 123101 and 123012; a comparator (CMP) 1244 whose first and second inputs are connected to the outputs of the respective adders 123011 and 123102; a selector 1251 whose first to third inputs are connected to the outputs of the adders 123001 and 123112 and the output of the comparator 1241 and one output of which is connected to a corresponding input of the writing port of the path memory 114; a selector 1252 whose first to third inputs are connected to the outputs of the adders 123111 and 123002 and the output of the comparator 1242 and one output of which is connected to a corresponding input of the writing port of the path memory 114; a selector 1253 whose first to third inputs are connected to the outputs of the adders 123101 and 123012 and the output of the comparator 1243 and one output of which is connected to a corresponding input of the writing port of the path memory 114; a selector 1254 whose first to third inputs are connected to the outputs of the adders 123011 and 123102 and the output of the comparator 1244 and one output of which is connected to a corresponding input of the writing port of the path memory 114; a flip-flop (FF) 1261 that is disposed between the other output of the selector 1251 and the other inputs of the adders 123001 and 123111; a flip-flop (FF) 1262 that is disposed between the other output of the selector 1252 and the other inputs of the adders 123101 and 123011; a flip-flop (FF) 1263 that is disposed between the other output of the selector 1253 and the other inputs of the adders 123112 and 123002; and a flip-flop (FF) 1264 that is disposed between the other output of the selector 1254 and the other inputs of the adders 123012 and 123102.
The maximum likelihood decision part 115 is composed of a counter 131 whose output is connected to the address input of the first reading port of the path memory 114, a shift register 128 whose output is connected to the address input of the second reading port of the path memory 114 and whose input is connected to the reading output of the path memory 114, a trace memory 129 whose input is connected to the output of the path memory 114 and that is disposed at the final stage, and an address controller 130 whose output is connected to the address input of the trace memory 129.
In the conventional example having the above configuration, a baseband signal is generated by a demodulator (not shown) for demodulating a received wave that has been received from a transmitting end through a radio transmission channel, the baseband signal being given as an array of code blocks that have been subjected, on the transmitting end, to xe2x80x9cinterleave processingxe2x80x9d (see FIG. 9(a)) for distribution on the time axis to prevent deterioration in transmission quality due to burst errors that may occur on the radio transmission channel.
In the de-interleaving part 111, the counter 117W generates write addresses by counting cyclically write clocks that are synchronized with the baseband signal. The counter 117R generates read addresses by counting read clocks (mentioned above) cyclically.
An array of code blocks (mentioned above) that are given as a baseband signal are sequentially written to storage areas of the dual port RAM 116 in a write address updating order (i.e., in the row direction) indicated by symbol (1) in FIG. 9(b).
The code blocks that have been written in the storage areas of the dual port RAM 116 in the above manner are sequentially read out in a read address updating order (i.e., in the column direction) indicated by symbol (2) in FIG. 9(b).
A bit string representing an array of code words read out from the dual port RAM 116 will be referred to simply as xe2x80x9creceived sequencexe2x80x9d and received signals at time point t is denoted by (ItQt). Although received signals (ItQt) may be represented by multiple values with soft decision, for the sake of simplicity it is assumed here that each of It and Qt is represented by a binary value, that is, xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
In the branch metric obtaining part 112, the branch metric computing units 12000, 12001, 12010, and 12011 compute, according to the following formulae, branch metrics (Hamming distances) xcex00(t), xcex01(t), xcex10(t),and xcex11(t) that represent differences between received signals (ItQt) at time point t and xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d, respectively, that are combinations of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d that are signals (branch signals) presumed in advance (to have been transmitted from a transmitting end):
xcex00(t)=(It⊕0)+(Qt⊕0)
xe2x80x83xcex01(t)=(It⊕0)+(Qt⊕1)
xcex10(t)=(It⊕r1)+(Qt⊕0)
xcex11(t)=(It⊕1)+(Qt⊕1)
where the symbol xe2x80x9c⊕xe2x80x9d means the operator of an exclusive-OR operation.
In the ACS-operation part 113, the adders 123001, 123111, 123101, 123011, 123112, 123002, 123012, and 123102 add a branch metric at time point tj that is produced by the branch metric obtaining part 112 to a path metric that is an accumulation value of branch metrics to time point ti that precedes and is closest to t=0 to tj. Further, the comparators 1241-1244 perform magnitude comparison (large or small) on prescribed combinations of results of the above additions. The selectors 1251-1254 select small metrics as effective path metrics, and the flip-flops 1261-1264 store those path metrics as path metric values to time point ti.
A history of the above selection procedure is recorded in the path memory 114.
An operation performed by the ACS-operation part 133 will be described in a specific manner with reference to FIGS. 10(a) and 10(b).
It is assumed here that a convolutional encoder provided in a transmitting end performs coding in which the rate R of the code is xc2xd and the constraint length K is 3 and its specific configuration is as shown in FIG. 12 (encoder 136).
In FIGS. 10(a) and 10(b), states S00-S11 represent values xe2x80x9c00xe2x80x9d to xe2x80x9c11xe2x80x9d that are stored in a shift register 1361 provided in the transmitting end, that is, in the encoder 136 of FIG. 12.
That is, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d signals that are transmission data to become objects of convolutional coding in the transmission end are sequentially input to the shift register 1361 and then subjected to prescribed exclusive-OR operations, whereby they are converted into a transmission signal that is a combination (ItQt) at time point t. The transmission signal is transmitted to a receiving end after being subjected to further processing such as modulation.
Paying attention to the operation of the shift register 1361, the values that are stored in accordance with input data vary sequentially, for example, start from initial values xe2x80x9c00xe2x80x9d and take values listed below, as a result of which process they will finally take one of four kinds of combinations xe2x80x9c00xe2x80x9d to xe2x80x9c11xe2x80x9d.
xe2x80x9c10xe2x80x9d (Data xe2x80x9c1xe2x80x9d is input, whereby xe2x80x9c1xe2x80x9d is newly stored in the shift register 1361 and the first initial data xe2x80x9c0xe2x80x9d is erased.)
xe2x80x9c11xe2x80x9d (Data xe2x80x9c1xe2x80x9d is further input, whereby xe2x80x9c1xe2x80x9d is newly stored in the shift register 1361 and the second initial data xe2x80x9c0xe2x80x9d is erased.)
Therefore, the shift register 1361 that is provided in the transmitting end can take the four kinds of states S00-S11.
FIG. 10(a) is a trellis diagram showing a process of estimating transitions between the states S00-S11 in the transmitting end in the receiving end. The ACS-operation part 103 performs a path metrics operation based on this trellis diagram.
The reason why there are only two states that can occur immediately after each state (see arrows in FIG. 10A) is that the data stored in the shift register 1361 are replaced by input data one by one.
In FIG. 10(a), numbers xe2x80x9c00xe2x80x9d to xe2x80x9c11xe2x80x9d that are associated with solid-line or broken-line arrows represent signals to be received at a receiving end when the state of the shift register 1361 at the transmitting end makes transitions in the directions of the arrows, and correspond to signals presumed in advance (branch signals; mentioned above).
In the ACS-operation part 113, the flip-flops 1261-1264 store path metrics for the respective states S00-S11.
When, for example, branch metrics xcex00(3) and xcex11(3) at time point t=3 are received from the respective branch metric computing units 12000 and 12011, the adder 123001 adds a path metric (a value stored in the flip-flop 1261) for the state S00 at time point t=2 to the branch metric xcex00(3). The adder 123112 adds a path metric (a value stored in the flip-flop 1263) for the state S01 at time point t=2 to the branch metric xcex11(3).
The comparator 1241 compares two addition results and the selector 1251 selects a smaller one of the addition results. The flip-flop 1261 holds the selected addition result as a path metric at t=3.
The path memory 114 holds, as an optimum prior state, a prior state (in this case, xe2x80x9c00xe2x80x9d or xe2x80x9c01xe2x80x9d as a suffix of S) indicating the selected state (S00 or S11 at t=2) in a storage area corresponding to the address xe2x80x9c00xe2x80x9d indicating the state S00 at time point t=3.
Similarly, a prior state of the state S00 at time point t=4 is held in a storage area corresponding to the address xe2x80x9c00xe2x80x9d at time point t=4. In this manner, prior-state numbers corresponding to respective states are held for each time point.
That is, path metrics operations are performed for all routes from the state S00 at t=0 to the state S00 at t=3. When transitions are made from two different states (in this case, S00 and S01) to the same state (in this case, S00), a route having a smaller path metric is selected as a more likely route. A selection result is held in the flip-flop 1261 as a path metric corresponding to the state S00 at t=3, and will be used in subsequent path metrics operations.
That is, in the above processing, since operations are performed efficiently by omitting operations for unnecessary path metrics, only one state transition route is selected as a route that reaches each state at each time point.
In the maximum likelihood decision part 115, the shift register 128, which is initialized for each code block (mentioned above), sequentially captures decoding results output by of the path memory 114 and supplies those to the path memory 114 as read addresses.
The counter 131 performs cyclically, for each code block, processing of decrementing the count value every time a subsequent time point t comes.
Among prior-state numbers that have been selected by the selectors 1251-1254 and written to storage areas corresponding to the respective states S00-S11 at each time point, the path memory 114 outputs a prior state number that corresponds to a time point that is indicated by an address that is supplied to the first reading port from the counter 131 and corresponds to a state (one of S00-S11) corresponding to an address (one of xe2x80x9c00xe2x80x9d to xe2x80x9c11xe2x80x9d) that is supplied to the second reading port from the shift register 128.
Not only are such prior-state numbers supplied to the shift register 128 but also their MSB is sequentially stored in the trace memory 129 as the decoding results.
The address controller 130 generates addresses that indicate an array of storage areas that is reverse in order to an array of storage areas of the trace memory 129 to which the above decoding results are written.
The trace memory 129 restores transmission information by sequentially reading out decoding results that were stored in advance in the storage areas indicated by the above addresses.
That is, an array of code blocks that are supplied as a baseband signal is subjected, in the de-interleaving part 111, to de-interleave processing that is reverse to interleave processing that was performed at the transmission end, and also subjected to efficient traceback processing (see FIG. 10(b)) and maximum likelihood decision processing according to a Viterbi algorithm under cooperation among the branch metric obtaining part 112, the ACS-operation part 113, the path memory 114, and the maximum likelihood decision part 115.
Therefore, in a radio transmission system that is required to provide a high transmission rate and high transmission quality, the hardware scale and the power consumption can be reduced and a desired coding gain can be obtained in a stable manner even if the transmission bandwidth is not sufficiently wide.
FIG. 11 shows the configuration of another exemplary receiving part that incorporates a Viterbi decoder.
The receiving part of FIG. 11 is different from that of FIG. 8 in that a branch metric obtaining part 112A is provided in place of the branch metric obtaining part 112 and an ACS-operation part 113A is provided in place of the ACS-operation part 113.
The branch metric obtaining part 112A is different, in configuration, from the branch metric obtaining part 112 shown in FIG. 8 in that the former is newly provided with selectors 12111, 12112, 12121, and 12122 each having four inputs that are directly connected to all the outputs of the branch metric computing units 12000, 12010, 12001, and 12011 and having outputs that are connected to the respective inputs of the ACS-operation part 113A; prior-state counters 1221 and 1222 each having a 2-bit output that is directly connected to the read address input of the ACS-operation part 113A; an encoder 1321 that is disposed between the output of the prior-state counter 1221 and the selection inputs of the selectors 12111 and 12112; an encoder 1322 that is disposed between the output of the prior-state counter 1222 and the selection inputs of the selectors 12121 and 12122; inverters 13311 and 13312that are disposed between the two outputs of the encoder 1321 and the corresponding selection inputs of the selector 12112, respectively; and inverters 13321 and 13322 that are disposed between the two outputs of the encoder 1322and the corresponding selection inputs of the selector 12121, respectively.
The ACS-operation part 113A is different, in configuration, from the ACS-operation part 113 shown in FIG. 8 in that adders 12311, 12312, 12321, and 12322 one inputs of which are connected to the outputs of the respective selectors 12111, 12112, 12121, and 12122 are provided in place of the adders (123001, 123002), (123011, 123012), (123101, 123102), and (123111, 123112); that the comparators 1243 and 1244, the selectors 1253 and 1254, and the flip-flops 1261-1264 are not provided; that the output of the adder 12311 is connected to one inputs of the comparator 1241 and the selector 1251; that the output of the adder 12321 is connected to the other inputs of the comparator 1241 and the selector 1251; that the output of the adder 12312 is connected to one inputs of the comparator 1242 and the selector 1252; that the output of the adder 12322 is connected to the other inputs of the comparator 1242 and the selector 1252; that a path metrics memory 126A is provided in place of the flip-flops 1261-1264 shown in FIG. 8 between one outputs of the respective selectors 1251 and 1252 and the other inputs of the adders 12311, 12312, 12321, and 12322; that a state counter 1341 is provided whose output is connected to the first write address input of the path metrics memory 126A and the address input of the first writing port of the path memory 114; and that a state counter 1342 is provided whose output is connected to the second write address input of the path metrics memory 126A and the address input of the second writing port of the path memory 114.
The encoder 1321 is composed of an exclusive-OR gate 13511 that is disposed as the final stage, whose first and second inputs are connected to the first and second outputs of the prior-state counter 1221, respectively, and whose third input is given a constant logical value xe2x80x9c0xe2x80x9d, and an exclusive-OR gate 13512 that is disposed as the final stage together with the exclusive-OR gate 13511, whose first input is connected to the second input of the prior-state counter 1221, and whose second input is given a constant logical value xe2x80x9c0xe2x80x9d.
The encoder 1322 is composed of an exclusive-OR gate 13521 that is disposed as the final stage, whose first and second inputs are connected to the first and second outputs of the prior-state counter 1222, respectively, and whose third input is given a constant logical value xe2x80x9c1xe2x80x9d, and an exclusive-OR gate 13522 that is disposed as the final stage together with the exclusive-OR gate 13521, whose first input is connected to the second input of the prior-state counter 1222, and whose second input is given a constant logical value xe2x80x9c1xe2x80x9d.
In the conventional example having the above configuration, the prior state counter 1221 that is provided in the branch metric obtaining part 112A outputs repeatedly and alternately at a prescribed rate 2-bit prior-state numbers corresponding to the respective states S00 and S10 (like xe2x80x9c00 xe2x80x9d, xe2x80x9c10 xe2x80x9d, xe2x80x9c00xe2x80x9d, . . . ) among the prior states S00, S10, S01, and S11 at a time point prior to a time point when the ACS-operation part 113A attempts to compute path metrics.
The prior state counter 1222 output repeatedly and alternately at the same rate 2-bit prior-state numbers corresponding to the respective states S01 and S11 (like xe2x80x9c01xe2x80x9d, xe2x80x9c11xe2x80x9d, xe2x80x9c01xe2x80x9d, . . . ) among the above-mentioned four states S00, S10, S01, and S11.
The above-mentioned rate is set in advance at two times a rate at which the branch metric computing units 12000, 12010, 12001, and 12011 compute branch metrics.
The encoders 1321 and 1322 and the inverters 13311, 13312, 13321, and 13322 generate branch numbers corresponding to four kinds of states, respectively, that are supplied alternately in an order of time-series from the prior-state counters 1221 and 1222 and cases where the value of a received sequence that is subsequently is given is xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, respectively.
For the sake of simplicity, it is assumed that such branch numbers conform to convolutional coding in which the rate R of the code is xc2xd and the constraint length K is 3.
The selectors 12111, 12112, 12121, and 12122 sequentially supplies the adders 12311, 12312, 12321, and 12322 with branch metrics corresponding to, on a trellis diagram, branches indicated by such a code sequence among branch metrics computed by the branch metric computing units 12000, 12010, 12001, and 12011.
In the ACS-operation part 113A, the state counters 1341 and 1342 output state numbers representing the respective states S00-S11 on a trellis diagram for every lapse, from a time point when the prior-state counters 1221 and 1222 updated the prior state numbers, of a time that is approximately equal to a propagation delay time (time required for operations) of a closed loop from the input ends of the adders 12311, 12312, 12321, and 12322 past the comparators 1241 and 1242, the selectors 1251 and 1252, and the path metrics memory 126A to the input ends of the adders 12311, 12312, 12321, and 12322.
The adders 12311, 12312, 12321, and 12322 add path metrics to branch metrics that are supplied from the branch metrics obtaining part 112A in a prior state corresponding to an address that is supplied by the prior-state counters 1221 and 1222 to the path metrics memory 126A. The comparators 1241 and 1242 compares results of those additions, causes storage, as a path metric of each state, of a smaller one of the two in a storage area of the path-metrics memory 126A that is indicated by an address that is supplied from the state counters 1341 and 1342, and causes storage of a history of such a selection procedure in the path memory 114 at each time point.
That is, in the Viterbi decoder shown in FIG. 8, many adders, comparators, etc. are needed for obtaining path metrics and selection histories at the same time for the above-mentioned four states. However, in the Viterbi decoder shown in FIG. 11, since path metrics operations and other operations relating to respective states are performed in a time-divisional manner in synchronism with the operations of the prior-state counters 1221 and 1222 and the state counters 1341, and 1342, the same components are shared by plural kinds of processing and hence the configuration can be simplified.
Incidentally, in each of the above conventional examples, since a decoding result obtained with the path memory 114 is one given as a result of the above-described traceback processing, it is a bit string that is arranged in order that is reverse to the order of transmission from the transmitting end to the transmission channel.
Therefore, to perform processing of again reversing the order of such a bit string, the maximum likelihood decision part 115 is provided with the trace memory 129 and the address controller 130, which are a factor of increasing the hardware scale.
Such processing takes not only an access time that is specific to the trace memory 129 but also a time corresponding to a difference between time points that conform to propagation delay times and response times specific to the ACS-operation part 113 or 113A and the maximum likelihood decision part 115 and when writing and reading are performed reliably on individual storage areas of the trace memory 129.
However, such a time corresponds to part of transmission delay times that inherently occur in a transmission system. Therefore, the higher the required transmission rate is, the more necessary it is to use high-speed devices to form the branch metric obtaining part 112 or 112A, the ACS-operation part 113 or 113A, the path memory 114, and the maximum likelihood decision part 115.
Further, in general, such high-speed devices consume more power than low-speed devices. Therefore, particularly in equipment such as portable communication terminal equipments, because of limitation is relating to the high-density mounting and the thermal designing, it is difficult to realize desired reduction in weight, size, and price and a desired continuous operation time unless changes in certain specifications or deterioration in performance is permitted.
An object of the present invention is to provide a Viterbi decoder and a transmitting equipment which make it possible to simplify the hardware configuration without deteriorating the transmission quality.
Another object of the invention is to restore transmission information without reversing on the time series as long as the state of the encoder is reliably set to a known initial state such as an all-zero state at both the starting and the ending point in time of the coding.
Another object of the invention is to heighten the decoding efficiency and increase the flexibility of configuration.
Another object of the invention is to simplify the hardware configuration.
Still another object of the invention is to make it possible to apply the invention to a receiving end irrespective of functional distribution with a transmitting end located on the other side of a transmission channel.
A further object of the invention is to make it possible to apply the invention to a receiving end without making the configuration more complex under the circumstance where the hardware for de-interleave processing conforming to interleave processing performed at the transmitting end performs another process.
Another object of the invention is to implement a receiving end with small-scale hardware.
Another object of the invention is to increase the flexibility relating to the standardization, designing, maintenance, and operation of equipment that constitutes a transmission system to which the invention is applied, and a attain reduction in running cost and increase in reliability without deteriorating the performance or service quality.
The above objects are attained by a Viterbi decoder in which path metrics are sequentially computed by adapting to a reverse trellis diagram obtained by reversing the order of time-series of a trellis diagram indicating, in the order of time-series, states that an encoder used for coding can be in, and in which decoding is performed by the ACS operation according to the computed path metrics.
In the above Viterbi decoder, each code block is decoded normally even in a case where it is supplied as a code word obtained by reversing the order of time-series of a bit string included in the code word in the above-described manner as long as the state of the encoder is reliably set to a known initial state such as an all-zero state at both the starting and the ending points in time of the coding. Transmission information is restored as an array of survivors without having the order of time-series reversed.
The above objects are attained by a Viterbi decoder which has an encoder that performs a reverse operation on the time series according to an ordinary trellis diagram, and in which path metrics corresponding to states (paths) that are given. as a code sequence obtained by the encoder are sequentially computed.
In the above Viterbi decoder, not only the decoding efficiency is heightened, but also the flexibility of configuration is increased.
The above objects are attained by a Viterbi decoder in which the above-mentioned code sequence is stored in advance as values adapted to a coding system used for the code sequence and is used in place of a code sequence supplied from the encoder.
In the above Viterbi decoder, ACS operations can be performed serially within the-range that the components can respond, and the configuration can be made simpler than in a case where the ACS operations are performed in parallel.
The above objects are attained by a Viterbi decoder in which the reversing of the order on the time series of a bit string of each of the code blocks that are given as a received sequence is restored prior to the computation of path metrics.
In the above Viterbi decoder, branch metrics can be computed even in a case where code words to be referred to for computation of the branch metrics are not supplied directly through the transmission channel.
The above objects are attained by a Viterbi decoder in which the processing of reversing the order of the time series of a bit string of each of code blocks is performed together with de-interleave processing that conforms to interleave processing that was performed at a transmitting end.
In the above Viterbi decoder, the configuration is simplified even when interleave processing is performed in a transmission system at the transmitting end, by using another section that performs de-interleave processing that conforms to the interleave processing at the receiving end.
The above objects are attained by a transmitting equipment which transmits, to a receiving equipment incorporating the above-described Viterbi decoder, transmission information that includes a bit sequence obtained by splitting transmission information into pieces having a prescribed word length and reversing the order on the time series after being subjected to a coding process that conforms to the Viterbi decoder.
Since processing that is equivalent to the reverse processing to be performed in the above-described Viterbi decoder is performed in the above transmitting equipment, the receiving end can incorporate the Viterbi decoder without enlarging the hardware scale.
The above objects are attained by a transmitting equipment which performs the processing of reversing the order of time series together with interleave processing.
With the above transmitting equipment, a transmitting system that conforms to a receiving end incorporating the above-described Viterbi decoder can be realized at a low cost without making the hardware configuration more complex.